MPC8540 datasheet(994/1302 Pages) FREESCALE

994 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-70

Freescale Semiconductor

RapidIO Interface

17.3.3.1.5 Outbound Destination Port Register (ODPR)

The destination port register (ODPR), shown in Figure 17-66, indicates the port to which the

message unit controller is to send data. Software must ensure that this is a valid port in the

receiving device.

Figure 17-66. Outbound Destination Port Registers (ODPR)

Table 17-68 describes the fields of the ODPR.

17.3.3.1.6 Outbound Destination Attributes Register (ODATR)

The outbound destination attributes register (ODATR) contains the transaction attributes to be

used for the message operation. Figure 17-67 shows the ODATR.

Figure 17-67. Outbound Destination Attributes Register (ODATR)

Table 17-69 describes the fields of the ODATR.

R 0

0 0

0 0000 00 000 00 00000 0000 0000 0

MAILBOX

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1018

Table 17-68. ODPR Field Descriptions

Bits

Name

Description

0–29

—

Reserved

30–31 MAILBOX Value for mbox field in message packet

11 12

15 16

21 22

29 30 31

R0 0

EOMIE

DTFLOWLVL

000 00 0

DWRITETTYPE

00 0 0 00

DTGTROUTE

Reset

0000_0000_0000_0110_0000_0000_0000_0000

Offset

0xD_101C

Table 17-69. ODATR Field Descriptions

Bits

Name

Description

0—

Reserved

—

Reserved, hardwired to 0.

EOMIE

End-of-message interrupt enable

0 End-of-message interrupt disabled

1 Generates an interrupt upon completion of the current message operation.

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