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MPC8540 Datasheet(PDF) 997 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 997 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-73
Figure 17-70. Inbound Mode Register (IMR)
Table 17-72 describes the fields of the IMR.
0
10
11
12
1516
1920
22
23
24
25
26
27
29 30
31
R 0 00000000 0 0
SEN
FRM_SIZ
CIRQ_SIZ
000
QFIE
0
MIQIE EIE
000
MI ME
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xD_1060
Table 17-72. IMR Field Descriptions
Bits
Name
Description
0–10
—
Reserved
11
SEN
Snoop enable
0 Snooping of the processor core while writing messages into memory disabled
1 Snooping of the processor core while writing messages into memory enabled
12–15
FRM_SIZ Message frame size. Determines the maximum message size that can be accepted by this
mailbox without error. This parameter combined with CIRQ_SIZ determine the maximum
contiguous memory space allocated to the mailbox.
0000–0001 Reserved
0010 8 bytes
0011 16 bytes
0100 32 bytes
0101 64 bytes
0110 128 bytes
0111 256 bytes
1000 512 bytes
1001 1024 bytes
1010 2048 bytes
1011 4096 bytes
1100–1111 Reserved
16–19
CIRQ_SIZ Circular frame queue size. Determines the number of message frames that can be placed in the
circular queue without overflow. This parameter combined with FRM_SIZ determines the
maximum contiguous memory space allocated to the mailbox.
0000 2
0001 4
0010 8
0011 16
0100 32
0101 64
0110 128 (4 Kbyte page boundary)
0111 256
1000 512
1001 1024
1010 2048
1011–1111 Reserved
20–22
—
Reserved
23
QFIE
Queue full interrupt enable
0 No QFI interrupt is generated
1 Generates an interrupt when the queue is full (that is, the enqueue and dequeue pointers are
equal after the dequeue pointer was incremented by the mailbox controller)
24
—
Reserved
25
MIQIE
Message in queue interrupt enable
0 No MIQ interrupt is generated
1 Generates an interrupt when the queue transitions to not empty (that is, the enqueue and
dequeue pointers are no longer equal after an increment by the mailbox controller)



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