MPC8540 datasheet(1000/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-76

Freescale Semiconductor

RapidIO Interface

Table 17-74 describes the fields of the IFQDPAR.

17.3.3.2.4 Inbound Frame Queue Enqueue Pointer Address Register

(IFQEPAR)

The inbound frame queue enqueue pointer address register (IFQEPAR), shown in Figure 17-73,

contains the address for the next message frame in memory to be added to the queue. Software

must initialize this register to match the frame queue dequeue pointer address. When the mailbox

controller receives a message, it writes the message data to the next location in the queue

(indicated by the address in IFQEPAR) and then increments IFQEPAR to point to the next frame

location in memory. This can result in the following:

•

If the enqueue and dequeue pointers match, the queue is now full and the mailbox controller

does not accept more incoming messages, returning RETRY responses to the sending

devices until the queue is no longer full. If IMR[QFIE] is set, then ISR[QFI] is set and an

interrupt is generated.

•

If the enqueue and dequeue pointer were the same before the register was read, the queue

has transitioned from empty to not empty. If IMR[MIQIE] is set, ISR[MIQI] is set and an

interrupt is generated.

Figure 17-73. Inbound Frame Queue Enqueue Pointer Address Registers (IFQEPAR)

Table 17-75 describes the fields of the IFQEPAR.

Table 17-74. IFQDPAR Field Descriptions

Bits

Name

Description

0–28

FQDPA Frame queue dequeue pointer address. Contains the address of the first message in memory to process

29–31

—

Reserved

28 29

FQEPA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1074

Table 17-75. IFQEPAR Field Descriptions

Bits

Name

Description

0–28

FQEPA Frame queue enqueue pointer address. Contains the address of the next message frame to be added to

the queue.

29–31

—

Reserved

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