MPC8540 datasheet(1003/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-79

17.3.3.3.3 Doorbell Queue/Dequeue Pointer Address Register (DQDPAR)

The doorbell queue dequeue pointer address register (DQDPAR), shown in Figure 17-76, contains

the double-word address for the first doorbell in memory to be processed. Software must initialize

this register to the first doorbell entry location in memory. When a current doorbell has been

processed, software sets DMR[DI]. The doorbell hardware then increments the DQDPAR to point

to the next doorbell in memory and clear DMR[DI].

If the doorbell queue enqueue pointer and the doorbell queue dequeue pointer are not equal

(indicating that the queue is not empty), software can read the next doorbell from memory for

processing. If the enqueue and dequeue pointers are equal after being incremented by software, the

queue is empty and all outstanding doorbells have been processed.

12–14

—

Reserved

DIQ

Doorbell-in-queue (read only)

0 No doorbell-in-queue conditions

1 If the queue goes from empty to not empty, this bit is set. Hardware clears this bit when software has

emptied the queue.

16–23

—

Reserved

Transaction error

0 There was no error condition during the doorbell operation.

1 There was an error condition during the doorbell operation. An interrupt is generated if DMR[IEI] is set.(Bit

reset, write-one-to-clear)

25–26

—

Reserved

QFI

Queue full interrupt

0 No queue full interrupt condition

1 The queue became full and the queue fill interrupt is enabled (IMR[QFIE] = 1). An interrupt is generated.

(Bit reset, write-one-to-clear).

—

Reserved

Doorbell busy (read only)

0 Cleared as a result of receiving an error or the completion of a doorbell operation

1 Indicates that a doorbell operation is currently in progress

—

Reserved

DIQI

Doorbell-in-queue interrupt

0 No doorbell-in-queue interrupt condition

1 The queue went from empty to not empty and OMR[DIQIE] is set. An interrupt is generated. (Bit reset,

write-one-to-clear)

Table 17-77. DSR Field Descriptions (continued)

Bits

Name

Description

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