MPC8540 datasheet(1004/1302 Pages) FREESCALE

1004 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-80

Freescale Semiconductor

RapidIO Interface

Figure 17-76. Doorbell Queue Dequeue Pointer Address Registers (DQDPAR)

Table 17-78 describes the fields of the DQDPAR.

17.3.3.3.4 Doorbell Queue Enqueue Pointer Address Register (DQEPAR)

The doorbell queue enqueue pointer address register (DQEPAR), shown in Figure 17-77, contains

the double-word address for the next doorbell entry in memory to be added to the queue. Software

must initialize DQEPAR to match the doorbell queue dequeue pointer address. When the doorbell

controller receives a packet, it writes the doorbell information to the next location in the queue

(indicated by the address in DQEPAR) and then increments DQEPAR to point to the next doorbell

location. This can result in the following:

•

If the enqueue and dequeue pointers match, then the queue is now full and the doorbell

controller does not accept any more incoming doorbell packets, returning RETRY

responses to the sending devices until the queue is no longer full. If DMR[QFIE] is set, then

DSR[QFI] is set and an interrupt is generated.

•

If the enqueue and dequeue pointer were the same before reading the register, the queue has

transitioned from empty to not empty. If DRM[MIQIE] is set, DSR[MIQI] is set and an

interrupt is generated.

Figure 17-77. Doorbell Queue Enqueue Pointer Address Register (DQEPAR)

28 29

DQDPA

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_146C

Table 17-78. DQDPAR Field Descriptions

Bits

Name

Description

0–28

DQDPA Doorbell queue dequeue pointer address. Contains the double-word address of the first doorbell in

memory to process.

29–31

—

Reserved

28 29

DQEPA

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1474

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