MPC8540 datasheet(1001/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-77

17.3.3.3 RapidIO Doorbell Registers

These registers control the RapidIO doorbell unit. The following sections provide descriptions of

these registers.

17.3.3.3.1 Doorbell Mode Register (DMR)

The doorbell mode register (DMR) allows software to enable the doorbell controller to control

various doorbell operation characteristics. Figure 17-74 shows the DMR.

Figure 17-74. Doorbell Mode Register (DMR)

Table 17-76 describes the fields of the DMR.

15 16

1920

2728 2930

R 0 000 000 000 0

SEN

0000

CIRQ_SIZ

000

QFIE

DIQIE EIE

000

DI DE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1460

Table 17-76. DMR Field Descriptions

Bits

Name

Description

0–10

—

Reserved

SEN

Snoop enable

0 Snooping of the processor core while writing doorbell information into memory disabled

1 Snooping of the processor core while writing doorbell information into memory enabled

12–15

—

Reserved

16–19

CIRQ_SIZ Circular doorbell queue size. Determines the number of doorbell entries that can be place in the

circular queue. CIRQ_SIZ*8 bytes determine the maximum contiguous memory space allocated

to the doorbell unit.

0000 2

0001 4

0010 8

0011 16

0100 32

0101 64

0110 128

0111 256

1000 512 (4-Kbyte page boundary)

1001 1024

1010 2048

1011–1111 Reserved

20–22

—

Reserved

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