MPC8540 datasheet(1002/1302 Pages) FREESCALE

1002 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-78

Freescale Semiconductor

RapidIO Interface

17.3.3.3.2 Doorbell Status Register (DSR)

The doorbell status register (DSR) reports various doorbell conditions after a doorbell operation.

Writing a 1 to the corresponding set bit clears it. Figure 17-75 shows the DSR.

Figure 17-75. Doorbell Status Register (DSR)

Table 17-77 describes the fields of the DSR.

QFIE

Queue full interrupt enable

0 No QFI interrupt generated

1 Generates an interrupt when the queue is full (that is, the enqueue and dequeue pointers are

equal after the dequeue pointer was incremented by the doorbell controller)

—

Reserved

DIQIE

Doorbell in queue interrupt enable

0 No DIQ interrupt generated

1 Generates an interrupt when the queue transitions to not empty (that is, the enqueue and

dequeue pointers are no longer equal after an increment by the doorbell controller)

EIE

Error interrupt enable

0 No interrupt is generated if a programming or transfer error is detected.

1 Generates an interrupt if a programming or transfer error is detected

27–29

—

Reserved

Doorbell increment. Software sets DI after processing an inbound doorbell. When software sets

DI, hardware increments the DQDPAR and clears DI. Always reads as 0 while DE is set

Doorbell enable

0 Doorbell disabled

1 The doorbell has been initialized and can service incoming doorbell operations.

1516

23 24

25 2627

28 29 30

R 0 00 0 0 0 0 000 0 QF 0

0 DIQ 000 000 00

QFI

0DB 0

DIQI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1464

Table 17-77. DSR Field Descriptions

Bits

Name

Description

0–10

—

Reserved

Queue full (read only)

0 Queue is not full

1 If the queue becomes full, this bit is set. Hardware clears this bit when software empties one or more entry.

Table 17-76. DMR Field Descriptions (continued)

Bits

Name

Description

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