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MPC8540 Datasheet(PDF) 1006 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1006 Page - Freescale Semiconductor, Inc |
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1006 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 17-82 Freescale Semiconductor RapidIO Interface 17.3.3.4.2 Port-Write Status Register (PWSR) The port-write status register (PWSR), shown in Figure 17-79, reports various port-write conditions after a port-write operation. Writing a 1 to a corresponding set bit clears the bit. Figure 17-79. Port-Write Status Register (PWSR) Table 17-81 describes the fields of the PWSR. 27–29 — Reserved 30 CQ Clear queue. Set by software after processing an inbound port-write operation. Hardware clears the previous port-write operation from the port-write queue and clears CC. Always reads as 0 if PWE = 1. 31 PWE Port-write enable 0 Port-writes are disabled. 1 The port-write controller has been initialized and can service an incoming port-write operation. 0 10 1112 23 2425 26 27 28 29 30 31 R 0 0000 0000 00 QF 0 0 00 00 00 00 00 TE 00 QFI 0PWB 0 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0xD_14E4 Table 17-81. PWSR Field Descriptions Bits Name Description 0–10 — Reserved 11 QF Queue full (read only) 0 The queue is not full. 1 The queue became full. 12–23 — Reserved 24 TE Transaction error 0 No transaction error occurred 1 There was an error condition (the port-write transaction is greater than 64 bytes) during the port-write operation. An interrupt is generated if PWMR[IEI] is set. (Bit reset, write-one-to-clear) 25–26 — Reserved 27 QFI Queue full interrupt. (Bit reset, write-one-to-clear) 0 Must be cleared by software after a port-write is serviced to re-enable the port-write controller 1 The queue became full and PWMR[QFIE] is set. An interrupt is generated. 28 — Reserved Table 17-80. PWMR Field Descriptions (continued) Bits Name Description |
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