Electronic Components Datasheet Search
  English  ▼

X  

MPC8540 Datasheet(PDF) 1006 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1006 Page - Freescale Semiconductor, Inc

Back Button MPC8540 Datasheet HTML 1002Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1003Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1004Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1005Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1006Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1007Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1008Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1009Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 1010Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 1006 / 1302 page
background image
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
17-82
Freescale Semiconductor
RapidIO Interface
17.3.3.4.2 Port-Write Status Register (PWSR)
The port-write status register (PWSR), shown in Figure 17-79, reports various port-write
conditions after a port-write operation. Writing a 1 to a corresponding set bit clears the bit.
Figure 17-79. Port-Write Status Register (PWSR)
Table 17-81 describes the fields of the PWSR.
27–29
—
Reserved
30
CQ
Clear queue. Set by software after processing an inbound port-write operation. Hardware clears the
previous port-write operation from the port-write queue and clears CC. Always reads as 0 if PWE = 1.
31
PWE
Port-write enable
0 Port-writes are disabled.
1 The port-write controller has been initialized and can service an incoming port-write operation.
0
10
1112
23 2425 26
27
28
29
30 31
R 0 0000 0000 00
QF
0 0 00 00 00 00 00
TE
00
QFI
0PWB 0
0
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xD_14E4
Table 17-81. PWSR Field Descriptions
Bits
Name
Description
0–10
—
Reserved
11
QF
Queue full (read only)
0 The queue is not full.
1 The queue became full.
12–23
—
Reserved
24
TE
Transaction error
0 No transaction error occurred
1 There was an error condition (the port-write transaction is greater than 64 bytes) during the
port-write operation. An interrupt is generated if PWMR[IEI] is set. (Bit reset, write-one-to-clear)
25–26
—
Reserved
27
QFI
Queue full interrupt. (Bit reset, write-one-to-clear)
0 Must be cleared by software after a port-write is serviced to re-enable the port-write controller
1 The queue became full and PWMR[QFIE] is set. An interrupt is generated.
28
—
Reserved
Table 17-80. PWMR Field Descriptions (continued)
Bits
Name
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com