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MPC8540 Datasheet(PDF) 1009 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1009 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
17-85
Table 17-84 summarizes packet formats. The following definitions and Figure 17-81 accompany
the table.
•
PMF—Physical maintenance field; prefixed to each packet format (see Figure 17-81)
•
TYPE —Packet type (1, 2, 5, 6, 8, 10, 11, 13)
•
TARID —target_id: the receiver’s ID within its domain
•
SRCTID— Packet transaction ID
•
TTYPE—Transaction type to be performed by the recipient
•
RDSIZE—Read data size requested
•
WRSIZE—Write data size requested
•
SRCID—source_id: the packet sender’s ID within its domain
•
ADDR—Address for the requested operation
•
MSB—Most-significant byte
•
LSB —Least-significant byte
•
HOPCNT—hop_count selects the distance into the switch network to access
•
CONFIG_OFFSET—Double-word offset into the CAR/CSR register file
•
INFO—Doorbell information field; provided and used by software only
•
MSGLEN—Total number of packets comprising the message
•
MSGSEG—Portion of the message supplied by the packet
•
SSIZE—Standard message packet data size
•
MBOX—Recipient mailbox number at the target device
•
LETTER—Identifies message within the mailbox
•
STATUS—Packet response status field
•
TARINFO—Target_info used for messages only. Field length is 8 bits:
letter (2) + mbox (2) + msgseg (4)
•
W—Word pointer; used in the decoding of the transaction size
11
Message
class
message
Message
passing
M = 0 write type operation
done, retry, error None
13
Response
class
response
All
N/A
Depends on the
request
Table 17-83. RapidIO Transaction Summary (continued)
Packet
Format
RapidIO
Transaction
Programming
Model
Possible Processor
Operations
Possible
RapidIO
Responses
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