MPC8540 datasheet(1008/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-84

Freescale Semiconductor

RapidIO Interface

Table 17-83. RapidIO Transaction Summary

Packet

Format

RapidIO

Transaction

Programming

Model

Possible Processor

Operations

Possible

RapidIO

Responses

Comments

Non-

intervention

request class

I/O read home

GSM

I = 1, M = 1 loads, and

instruction fetches where the

target of the request is a remote

address space. M = 0 read type

operations may also map to I/O

read home.

done,

(data_only +

done_interv)

retry, error

None

Non-

intervention

request class

nread

M = 0 read type operations

where the target of the request

is a remote address space

done, error

None

atomic

M = 0 read type mapped

operation

done, error

Atomic transactions

should map in the

ATMU to the DDR

memory controller, or

the behavior is

boundedly

undefined.

Write class

flush (with data)

GSM

M = 1, W = 1 or I = 1, store.

M = 0 store type operation may

also map to flush.

done, retry, error None

atomic swap

N/A

The RapidIO

controller does not

support atomic swap

transactions.

nwrite

M = 0 store type operation

N/A

None

nwrite_r

M = 0 store type operation

done, error

None

Streaming

write class

swrite

M = 0 store type operation

N/A

None

Maintenance

class

maintenance

read

All

M = 0 read type operation

done, error

Although possible,

maintenance reads

from memory

locations outside of

the RapidIO

architectural memory

space (0xC_0000–

0xC_FFFC) return

unreliable data.

maintenance

write

All

M = 0 write type operation

done, error

None

Doorbell class

doorbell

Message

passing

M = 0 write type operation

done, retry, error None

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