MPC8540 datasheet(1007/1302 Pages) FREESCALE

1007 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-83

17.3.3.4.3 Port-Write Queue Base Address Register (PWQBAR)

The port-write queue base address register (PWQBAR), shown in Figure 17-80, contains the

64-byte cache line address for the port-write data payload. PWQBAR must be initialized by

software.

Figure 17-80. Port-Write Queue Base Address Register (PWQBAR)

Table 17-82 describes the fields of the PWQBAR.

17.4 Functional Description

The following sections provide summaries of RapidIO transactions, packets and control symbols.

Additional information may be found in the Parallel RapidIO Interconnect Specification.

17.4.1 RapidIO Transaction, Packet, and Control Symbol Summary

Table 17-83 summarizes the RapidIO transaction types supported by the RapidIO controller. The

table lists the packet format type, the RapidIO transaction, the transaction programming model,

the processor operations that may cause the RapidIO transaction, possible responses for the

transactions, and comments that note RapidIO-specific details associated with the transaction, or

response. Transactions that are not supported by the RapidIO implementation are noted in the

comments section of Table 17-83.

PWB

Port-write busy (read only)

0 Cleared as a result of receiving an error or upon the completion of a port-write operation

1 Indicates that a port-write operation is currently in progress

30–31

—

Reserved

25 26

PWQBA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_14EC

Table 17-82. PWQBAR Field Descriptions

Bits

Name

Description

0–25

PWQBA Port-write queue base address. Contains the cache line address of the port-write data payload.

26–31

—

Reserved

Table 17-81. PWSR Field Descriptions (continued)

Bits

Name

Description

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