MPC8540 datasheet(1005/1302 Pages) FREESCALE

1005 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-81

Table 17-79 describes the fields of the DQEPAR.

17.3.3.4 RapidIO Port-Write Registers

These registers control the RapidIO port-write unit. The following sections describe these

registers. Additional information may be found in the Parallel RapidIO Interconnect

Specification.

17.3.3.4.1 Port-Write Mode Register (PWMR)

The port-write mode register (PWMR) allows software to enable the port-write controller and to

control various port-write operation characteristics. Figure 17-78 shows the PWMR.

Figure 17-78. Port-Write Mode Register (PWMR)

Table 17-80 describes the fields of the PWMR.

Table 17-79. DQEPAR Field Descriptions

Bits

Name

Description

0–28

DQEPA Doorbell queue enqueue pointer address. Contains the double-word address of the next doorbell

location to be added to the queue

29–31

—

Reserved

101112

24 25

R 0 0 0 0 0 0 0 0 0 0 0

SEN

0 0 0 0 0 0 0 0 0 0 0

QFIE

EIE

0 0 0

CQ PWE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_14E0

Table 17-80. PWMR Field Descriptions

Bits

Name

Description

0–10

—

Reserved

SEN

Snoop enable

0 Snooping the processor core while writing port-write data payload into memory disabled

1 Snooping the processor core while writing port-write data payload into memory enabled

12–22

—

Reserved

QFIE

Queue full interrupt enable

0 No QFI interrupt generated

1 Generates an interrupt when the queue becomes full (that is, the controller has written a port-write

data payload into memory)

24–25

—

Reserved

EIE

Error interrupt enable

0 No interrupt is generated if a programming or transfer error is detected.

1 Generates an interrupt if a programming or transfer error is detected

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