MPC8540 datasheet(999/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-75

17.3.3.2.3 Inbound Frame Queue Dequeue Pointer Address Register

(IFQDPAR)

The inbound frame queue dequeue pointer address register (IFQDPAR), shown in Figure 17-72,

contains the address for the first message in memory to be processed. Software must initialize this

IMR[MI]. The mailbox controller then increments IFQDPAR to point to the next frame in memory

and clears MI. If the inbound frame queue enqueue pointer and the inbound frame queue dequeue

pointer are not equal (indicating that the queue is not empty), software can read the next message

frame from memory for processing. If the enqueue and dequeue pointers are equal after being

incremented by software, the queue is empty and all outstanding messages have been processed.

Figure 17-72. Inbound Frame Queue Dequeue Pointer Address Registers (IFQDPAR)

Transaction error

0 No transaction error

1 Set when there is an error condition during the message operation. An interrupt is generated if

IMR[IEI] is set. (Bit reset, write-one-to-clear)

25–26

—

Reserved

QFI

Queue full interrupt. (Bit reset, write-one-to-clear)

0 No queue full interrupt condition

1 If the queue becomes full and IMR[QFIE] is set, this bit is set and an interrupt is generated.

—

Reserved

Mailbox busy (read only)

0 Cleared as a result of receiving an error or the completion of a message operation

1 When set indicates that a message operation is currently in progress.

—

Reserved

MIQI

Message-in-queue interrupt. (Bit reset, write-one-to-clear)

0 No message-in-queue interrupt condition

1 If the queue goes from empty to not empty and IMR[MIQIE] is set, this bit is set and an interrupt is

generated.

28 29

FQDPA

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_106C

Table 17-73. ISR Field Descriptions (continued)

Bits

Name

Description

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