MPC8540 datasheet(996/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-72

Freescale Semiconductor

RapidIO Interface

17.3.3.1.8 Outbound Descriptor Queue Enqueue Pointer Address Register

(ODQEPAR)

The outbound descriptor queue enqueue pointer address register (ODQEPAR), shown in

Figure 17-69, contains the address for the next descriptor in memory to be added to the queue.

Software must initialize this register to match the outbound descriptor queue dequeue pointer

address. If a message is ready to be sent, software writes a descriptor to the next location in the

queue (indicated by the address in ODQEPAR), and then should set OMR[MUI]. The message unit

then increments ODQEPAR to point to the next descriptor location in memory and clears

OMR[MUI]. This can result in a number of actions:

•

If the enqueue and dequeue pointers match, the queue is now full. If OMR[QFIE] is set,

then OSR[QFI] is set, and an interrupt is generated.

•

If the enqueue and dequeue pointer no longer match after the enqueue pointer has been

incremented and the queue is full, then the queue overflows, and the message unit stops. If

OMR[QOIE] is set, OSR[QOI] is set and an interrupt is generated.

•

If the enqueue and dequeue pointer are the same before reading the register and no overflow

condition is detected, the message unit controller starts (if enabled).

Figure 17-69. Outbound Descriptor Queue Enqueue Pointer Register (ODQEPAR)

Table 17-71 describes the fields of the ODQEPAR.

17.3.3.2 RapidIO Inbound Message Registers

Registers in this section describe the RapidIO inbound message registers.

17.3.3.2.1 Inbound Mode Register (IMR)

The inbound mode register (IMR) allows software to enable the mailbox controller and to control

various message operation characteristics. Figure 17-70 shows the IMR.

26 27

DQEPA

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1028

Table 17-71. ODQEPAR Field Descriptions

Bits

Name

Description

0–26

DQEPA Descriptor queue enqueue pointer address. Contains the address of the last descriptor in memory to

process. The descriptor must be aligned to a 32-byte boundary.

27–31

—

Reserved

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