MPC8540 datasheet(992/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-68

Freescale Semiconductor

RapidIO Interface

17.3.3.1.3 Outbound Descriptor Queue Dequeue Pointer Address Register

(ODQDPAR)

The outbound descriptor queue dequeue pointer address register (ODQDPAR), shown in

Figure 17-64, contains the address of the first descriptor in memory to be processed. Software

must initialize this register to point to the first descriptor in memory. After processing this

descriptor, the message unit controller increments the outbound descriptor queue dequeue pointer

address (ODQDPAR[DQDPA] to point to the next descriptor. If the outbound descriptor queue

enqueue pointer and the outbound descriptor queue dequeue pointer are not equal (indicating that

the queue is not empty), the message unit controller reads the next descriptor from memory for

processing. If the pointers are equal after the dequeue pointer has been incremented, the queue is

empty and the message unit halts until the enqueue pointer is incremented by software.

Incrementing the pointer indicates that a new descriptor has been added to the queue and is ready

for processing. If the queue becomes empty and OMR[QEIE] is set, OSR[QEI] is set and an

interrupt is generated.

QOI

Queue overflow interrupt. Only applicable to chaining mode. (Bit reset, write-one-to-clear)

0 No overflow interrupt condition

Queue overflow is detected and OMR[QOIE] is set. An interrupt is generated in this case

QFI

Queue full interrupt. Only applicable to chaining mode. (Bit reset, write-one-to-clear)

0 No queue full interrupt

1 The queue became full and OMR[QFIE] is set. An interrupt is generated in this case.

—

Reserved

MUB

Message unit busy (read-only)

0 Message unit not busy. Cleared when the message unit is no longer busy

1 A message operation is currently in progress.

EOMI

End-of-message interrupt. (Bit reset, write-one-to-clear)

0 No end-of-message interrupt condition

1 After finishing this message operation, if ODATR[EOMIE] is set, EOMI is set and an interrupt is

generated

QEI

Queue empty interrupt. Only applicable to chaining mode. (Bit reset, write-one-to-clear)

0 No queue empty interrupt condition

1 When the last message operation in the outbound descriptor queue is finished, if OMR[QEIE] is

set, then this bit is set and an interrupt is generated. Otherwise, no interrupt is generated.

Table 17-65. OSR Field Descriptions (continued)

Bits

Name

Description

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