MPC8540 datasheet(998/1302 Pages) FREESCALE

998 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-74

Freescale Semiconductor

RapidIO Interface

17.3.3.2.2 Inbound Status Register (ISR)

The inbound status register (ISR), shown in Figure 17-71, reports mailbox conditions during and

after a message operation. Writing a 1 to a writable condition bit in ISR clears it.

Figure 17-71. Inbound Status Register (ISR)

Table 17-73 describes the fields of the ISR.

EIE

Error interrupt enable

0 No interrupt is generated if a programming or transfer error is detected.

1 Generates an interrupt if a programming or transfer error is detected

27–29

—

Reserved

Mailbox increment. Software sets MI after processing an inbound message. When software sets

this bit, hardware increments the IFQDPAR and clears this bit. Always reads as 0 while ME is set

Mailbox enable

0 Mailbox disabled

1 The mailbox has been initialized and can service incoming message operations.

141516

25 26

R 0000000000 0 QF 000MIQ 0 000000 0

QFI

0MB 0

MIQI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xD_1064

Table 17-73. ISR Field Descriptions

Bits

Name

Description

0–10

—

Reserved

Queue full (read only)

0 Queue is not full

1 If the queue becomes full, this bit is set. Hardware clears this bit when software empties one or more

entries.

12–14

—

Reserved

MIQ

Message-in-queue (read only)

0 No message in queue

1 If the queue goes from empty to not empty, this bit is set. Hardware clears this bit when software has

emptied the queue.

16–23

—

Reserved

Table 17-72. IMR Field Descriptions (continued)

Bits

Name

Description

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