MPC8540 datasheet(959/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-35

Table 17-31 describes the fields of the CR.

17.3.2.1.2 Port Configuration Register (PCR)

The PCR contains configuration information regarding port behavior of the RapidIO controller.

Figure 17-28 shows the PCR.

Figure 17-28. Port Configuration Register (PCR)

Table 17-32 describes the fields of the PCR.

17.3.2.1.3 Port Error Injection Register (PEIR)

RapidIO error injection registers, shown in Figure 17-29, offer a simple way to inject errors into

an outbound packet or a control symbol. The error injection register for the target port is loaded

with control information for injecting an error in a packet stream or control symbol. After the

reaching that number, an error is injected in the specified byte using the byte mask. The error is

Table 17-31. CR Field Descriptions

Bits

Name

Description

0–30

—

Reserved

Accept all. Note: Must initially be cleared by the user as part of initialization

0 Detect an error upon receiving a packet with a target ID not equal to its own

1 All packets are accepted without checking the target ID.

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCE

0 0

Reset

0000_0000_0000_0000_0000_0000_0001_0000

Offset

0xD_0010

Table 17-32. PCR Field Descriptions

Bits

Name

Description

0–26

—

Reserved

CCE

CRC checking enable. Note that a read that attempts to access an unmapped target causes the

assertion of core_fault_in, which causes the core to generate a machine check interrupt, unless it is

disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, PCR[CCE] must be set to

ensure that an interrupt is generated. For more information, see Section 6.10.2, “Hardware

Implementation-Dependent Register 1 (HID1).”

0 No CRC is checked on received packets.

1 CRC is checked on received packets.

28–31

—

Reserved

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