MPC8540 datasheet(958/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-34

Freescale Semiconductor

RapidIO Interface

17.3.2 Implementation Registers

Following are the RapidIO implementation registers. These are registers specific to this particular

RapidIO implementation and, therefore, do not appear in the Parallel RapidIO Interconnect

Specification.

17.3.2.1 General Registers

17.3.2.1.1 Configuration Register (CR)

The CR contains configuration information regarding the behavior of the RapidIO controller.

Figure 17-27 shows the CR.

IPE

Input port receive enable. Must equal the value of PCCSR[OPE] for the RapidIO controller to function

properly

0 Port is stopped and only enabled to receive maintenance requests packets. Other requests return

packet-not-accepted control symbols with ‘General error’ cause to force an error condition to be

signalled by the sending device

1 Port is enabled to issue any packets

IPD

Input port receivers disable

0 Input receiver and/or output driver are enabled

1 Both the input receivers and output drivers are disabled.

7—

Reserved

ECD

Error checking disable. Disables all RapidIO transmission error checking

0 Error checking and recovery is enabled.

1 Error checking and recovery is disabled. Device behavior while error checking is disabled and an

error condition occurs is undefined.

9–31

—

Reserved

R 0

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset

0xD_0000

Figure 17-27. Configuration Register (CR)

Table 17-30. PCCSR Field Descriptions (continued)

Bits

Name

Description

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