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MPC8540 Datasheet(PDF) 946 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 946 Page - Freescale Semiconductor, Inc |
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946 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 17-22 Freescale Semiconductor RapidIO Interface 17.3.1.9 Mailbox Command and Status Register (MSR) The MSR, shown in Figure 17-11, reflects the status of the RapidIO mailbox controller on this device. Note that the RapidIO controller only supports Mailbox 0. Table 17-15 describes the fields of the MSR. 17.3.1.10 Port-Write and Doorbell Command and Status Register (PWDCSR) The PWDCSR, shown in Figure 17-12, reflects the status of the RapidIO doorbell and port-write hardware on this device. Additional details can be found in the Parallel RapidIO Interconnect Specification in the sections titled “Doorbell CSR” and “Write Port CSR.” 01 2 3 4 5 6 31 R A FU EM B 0 ERR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0xC_0040 Figure 17-11. Mailbox Status Register (MSR) Table 17-15. MSR Field Definitions Bits Name Description 0 A Available 0 Mailbox 0 is not ready to accept messages. All incoming message transactions return error responses. 1 Mailbox 0 is initialized and ready to accept messages. 1FU Full 0 Mailbox 0 is not full. 1 Mailbox 0 is full. New messages are retried. 2EM Empty 0 Mailbox 0 contains outstanding messages. 1 Mailbox 0 contains no outstanding messages. 3B Busy 0 Mailbox 0 is not busy processing a message. 1 Mailbox 0 is busy processing a message. New message operations return retry responses. 4— Reserved 5ERR Error 0 Mailbox 0 has not received an illegal message operation. 1 Mailbox 0 received an illegal message operation. All incoming message transactions return error responses. 6–31 — Reserved |
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