MPC8540 datasheet(1079/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-1

Chapter 19

Performance Monitor

This chapter describes the MPC8540 performance monitor facility, which can be used to monitor

and optimize performance. The e500 core implements a separate performance monitor for strictly

core-related behavior, such as instruction timing and L1 cache operations. This is described in the

e500 Reference Manual.

Section 19.4.7, “Performance Monitor Events,” briefly describes the events that can be monitored.

Refer to the individual chapters for a better understanding of these events.

19.1 Introduction

The MPC8540 includes a performance monitor facility that can be used to monitor and record

selected behaviors of the integrated device. Although the performance monitor described here is

similar in many respects to the performance monitor facility implemented on the e500 core, it

differs in that it is implemented using memory-mapped registers and it counts events outside the

e500 core, for example, RapidIO, PCI, DDR, and L2 cache events.

Performance monitor counters (PMC0–PMC8) are used to count events selected by the

performance monitor local control registers. PMC0 is a 64-bit counter specifically designated to

count cycles. PMC1–PMC8 are 32-bit counters that can monitor 64 counter-specific events in

addition to counting 64 reference events.

The benefits of the on-chip performance monitor are numerous and include the following:

•

Because some systems or software environments are not easily characterized by signal

traces or benchmarks, the performance monitor can be used to understand the MPC8540’s

behavior in any system or software environment.

•

The performance monitor facility can be used to aid system developers when bringing up

and debugging systems.

•

System performance can be increased by monitoring memory hierarchy behavior. This can

help to optimize algorithms used to schedule or partition tasks and to refine the data

structures and distribution used by each task.

19.1.1 Overview

Figure 19-1 is a high-level block diagram of the performance monitor, which consists of a global

control register (PMGC0), one 64-bit counter (PMC0), eight 32-bit counters, and two control

registers per counter (18 total control registers). The global control register PMGC0 affects all

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