MPC8540 datasheet(1077/1302 Pages) FREESCALE

1077 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-29

Lock bit of the PCI Bus Function Register so that the device will not respond to configuration

transactions. Upon exiting sleep mode, software should return these configuration bits to their

normal state.

18.5.2 General-Purpose I/O Signals

Several groups of signals can optionally be used as general-purpose I/O signals when not being

used for their primary function. The general-purpose I/O functionality of these signals can be

enabled through configuration registers in the global utilities block. These signals are the

following:

•

PCI_AD[47:40] and PCI_AD[39:32]. When configured as general-purpose I/O,

PCI_AD[47:40] function as outputs and PCI_AD[39:32] function as inputs.

PCI_AD[47:32] can be used as general-purpose I/O if the PCI/PCI-X interface is disabled

or if the PCI/PCI-X controller is not in 64-bit mode.

•

TSEC2_RxD[0:7] and TSEC2_TxD[0:7]. TSEC2 pins are fixed as either inputs or outputs

based on the direction of the signal’s primary function. The TSEC2_TxD pins are always

outputs, so these signals may only be used as outputs when configured as general-purpose

I/O. Similarly, the TSEC2_RxD pins are used as inputs when configured as

general-purpose I/O.

The TSEC2 TxD and RxD pins are available when the TSEC2 block is disabled. The TxD

signals can then be enabled as general-purpose outputs and the RxD pins can be enabled as

general-purpose inputs.

When configured as general-purpose I/O signals, software can read inputs by reading the

associated GPIO data register. Output values can be set by writing the to the associated GPIO data

Section 18.4.1.7, “General-Purpose I/O Control Register (GPIOCR).”

18.5.3 Interrupt and Local Bus Signal Multiplexing

The MPC8540 has very little signal multiplexing. Two sets of DMA channel triggering signals can

alternately be placed on other signals as follows:

•LCS[5:7] are multiplexed with DMA channel 2 DMA_DREQ2, DMA_DACK2, and

DMA_DONE2.

•

IRQ[9:11] are multiplexed with DMA channel 3 DMA_DREQ3, DMA_DACK3, and

DMA_DDONE3.

For details regarding the selection of the alternate function DMA trigger, see Section 18.4.1.10,

“Alternate Function Signal Multiplex Control Register (PMUXCR).”

MPC8540 Datasheet(PDF) 1077 Page - Freescale Semiconductor, Inc