MPC8540 datasheet(1080/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

19-2

Freescale Semiconductor

Performance Monitor

counters and takes priority over local control registers. The local control registers are divided into

two groups as follows:

•

Local control A registers control counter freezing, overflow condition enable, event

selection, and burstiness. Local control register PMLCA0, which controls counter PMC0,

does not contain event selection because PMC0 counts only cycles.

•

Local control B registers control the start and stop triggering, contain the counters’

threshold values, and the value of the threshold multiplier. Local control register PMLCB0,

which controls PMC0, does not contain threshold information because PMC0 only counts

cycles.

Figure 19-1. Performance Monitor Block Diagram

NOTE

Note that the performance monitor implemented on the core also uses

registers named PMCn and PMLCxn; however, these registers are

implemented on-chip, they are accessed using the EIS-defined mtpmr

and mtpmr instructions, and they do not interact with the

memory-mapped registers shown in Figure 19-1.

Performance monitor events are signalled by the functional blocks in the integrated device and are

selectively recorded in the PMCs. Sixty-four of these events are referred to as reference events,

Counters

Global Control Register

PMGC0

PMLCA3

PMLCB3

PMLCA2

PMLCB2

PMLCA1

PMLCB1

PMLCA0

PMLCB0

PMC1

PMC2

PMC3

...

Control Logic

Counters and Registers

Performance Monitor

Event 1

Event 2

Event 8

Event 3

Event 4

...

Event Signals

Interrupt (int)

Read Data

Output Signals

PMC8

PMLCA8

PMLCB8

Event 0

PMC0 (upper)

PMC0 (lower)

32-bit

Local Control Registers

...

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