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MPC8540 Datasheet(PDF) 1081 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1081 Page - Freescale Semiconductor, Inc

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External Signal Descriptions
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
19-3
which can be counted on any of the eight counters. Counter-specific events can be counted only
on the counter where the event is defined.
The performance monitor can generate an interrupt on overflow. Several control registers specify
how a performance monitor interrupt is signalled. The PMCs can also be programmed to freeze
when an interrupt is signalled.
19.1.2 Features
The MPC8540 performance monitor offers a rich set of features that permits a complete
performance characterization of the implementation. These features include:
•
One 64-bit counter exclusively dedicated to counting cycles
•
Eight 32-bit counters that count the occurrence of selected events
•
One global control register (affects all counters) and two local control registers per counter
•
Ability to count up to 64 reference events that may be counted on any of the eight 32-bit
counters
•
Ability to count up to 512 counter-specific events
•
Triggering and chaining capability
•
Duration threshold counting
•
Burstiness feature that permits counting of burst events with a programmable time between
bursts
•
Ability to generate an interrupt on overflow
19.2 External Signal Descriptions
The performance monitor does not have any signals that are driven externally (off-chip) but it does
assert the internal interrupt (int) signal on a performance monitor interrupt condition.
19.3 Memory Map and Register Definition
Performance monitor registers reside in the run-time register block starting at offset 0xE_1000.
This section describes the registers implemented to support the performance monitor facilities.
Table 19-1 lists the performance monitor registers. These registers can be read or written only with
32-bit accesses.
19.3.1 Register Summary
The performance monitor uses nine counter registers and a group of local control registers that are
used to specify the method of counting. Two local control registers are associated with each
counter in addition to a global control register that applies to all counters.



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