MPC8540 datasheet(1083/1302 Pages) FREESCALE

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Memory Map and Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-5

19.3.2 Control Registers

This section describes the performance monitor control registers in detail.

19.3.2.1 Performance Monitor Global Control Register (PMGC0)

The performance monitor global control register (PMGC0), shown in Figure 19-2, is a 32-bit

Figure 19-2. Performance Monitor Global Control Register (PMGC0)

Table 19-2 describes PMGC0 fields.

19.3.2.2 Performance Monitor Local Control Registers

(PMLCAn and PMLCBn)

The performance monitor local control registers (PMLCAn and PMLCBn) are used to control the

operation of the PMCs. The performance monitor local control A and B registers are paired 32-bit

control registers that are associated with an individual counter to specify how the counter is used

and what event is monitored on that counter. Figure 19-3 shows the performance monitor local

control A0 register (PMLCA0).

FAC PMIE FCECE

0000 0000000 0000000 0000000 0000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_1000

Table 19-2. PMGC0 Field Descriptions

Bits

Name

Description

FAC

Freeze all counters.

0 PMCs are incremented (if permitted by other PMGC0/PMLC bits).

1 PMCs are not incremented. Set by hardware when an interrupt is signalled and FCECE =1

PMIE

Performance monitor interrupt enable. Interrupts are caused by PMC overflows.

0 Interrupts are disabled.

1 Interrupts are enabled and occur when an enabled condition or event occurs.

FCECE

(DISCOUNT)

Freeze counters on enabled condition or event. An enabled condition or event is defined as:

The msb = 1 in PMCn and PMLCAn[CE] = 1.

The use of the trigger and freeze counter conditions depends on the enabled condition.

0 PMCs can be incremented (if permitted by other control bits).

1 PMCs can be incremented (if permitted by other control bits) only until an enabled condition

or event occurs, at which time PMGC0[FAC] is set. It is up to software to clear FAC.

3–31

—

Reserved

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