MPC8540 datasheet(1087/1302 Pages) FREESCALE

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Memory Map and Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-9

19.3.3 Counter Registers

This section describes the PMCs in detail.

NOTE

Because accessing a PMC manually has priority over incrementing it

due to event counting, reading or writing a PMC while it is counting

may affect the count. Likewise, accessing a performance monitor

control register while its target counter is counting may also affect the

count.

19.3.3.1 Performance Monitor Counters (PMC0–PMC8)

PMC0–PMC8 are used to count events selected by the performance monitor local control

registers. PMC0, shown in Figure 19-7, is associated with two 32-bit registers that form a 64-bit

counter designated to count clock cycles. PMC0 upper represents the upper 32 bits of counter 0,

and PMC0 lower represents the lower 32 bits.

14–15

TRIGOFFCNTL Trigger-off control. Indicates the condition under which triggering to stop occurs

00 Trigger off (no triggering to stop)

01 Trigger on change

10 Trigger on overflow

11 Reserved

16–20

—

Reserved

21–23

TBMULT

Threshold and burstiness multiplier. Threshold events are counted when the event duration

exceeds a specified threshold value. The threshold is scaled based on the TBMULT settings.

The burst distance for burstiness counting is also scaled using the TBMULT settings. For all

events that scale the threshold, the threshold field is multiplied by the factors shown below

(ranging from 1 to 128).

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

24–25

—

Reserved

26–31

THRESHOLD

Threshold. Only events whose (number of) occurrences exceed this value are counted. By

varying the threshold value, software can characterize the events subject to the threshold.

For example, if PMC2 counts TSEC BD read latencies for which the duration exceeds the

threshold, software can obtain the distribution of TSEC BD read latencies for a given program

by monitoring the program repeatedly using a different threshold value each time.

Table 19-6. PMLCBn Field Descriptions (continued)

Bits

Name

Description

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