MPC8540 datasheet(1089/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

19-11

freeze-counters-on-enabled-condition-or-event bit (PMGC0[FCECE]) is set, PMGC0[FAC] is set

by hardware and all of the registers are frozen. Software can clear the interrupt condition by

resetting the performance monitor and clearing the most significant bit of the counter that

generated the overflow.

19.4.2 Event Counting

Using the control registers described in Section 19.3.2, “Control Registers,” the nine PMCs can

count the occurrences of specific events. The 64-bit PMC0 is designated to count only clock

cycles. However, to provide flexibility, a total of 64 reference events can be counted on any of the

32-bit PMCs (PMC1–PMC8). Additionally, up to 64 unique events can be counted on each 32-bit

counter.

The performance monitor must be reset before event counting sequences. The performance

monitor can be reset by first freezing one or more counters and then clearing the freeze condition

to allow the counters to count according to the settings in the performance monitor

registers.þCounters can be frozen individually by setting PMLCAn[FC] bits, or simultaneously by

setting PMGC0[FAC]. Simply clearing these freeze bits will then allow the performance monitor

to begin counting based on the register settings.þ

Note that using PMLCAn[FC] to reset the performance monitor resets only the specified counter.

Performance monitor registers can be configured through reads or writes while the counters are

frozen as long as freeze bits are not cleared by the register accesses.

19.4.3 Threshold Events

The threshold feature allows characterization of events that can take a variable number of clock

cycles to occur. Threshold events are counted only if the latency is greater than the threshold value

specified in PMLCBn[THRESHOLD].

For duration threshold event sequences, the PMC increments only when the duration of the event

is equal to or greater than the threshold value. The threshold value is scaled by a multiple specified

in PMLCBn[TBMULT].

A threshold event requires two signals: The first indicates when a threshold event sequence begins,

and the second indicates when it ends. An internal counter determines when the threshold count is

exceeded and when the PMC can increment. This internal counter decrements during a threshold

event sequence until it reaches the value of one. A new sequence cannot begin until the current one

completes. Additional threshold start signals are ignored during a sequence until a threshold stop

signal occurs. If both a start and stop signal are asserted during the same cycle in a current

sequence, the stop terminates the current sequence and the start signals the beginning of a new one.

However, if both signals are asserted during the same cycle while not in a current event sequence,

both signals are ignored. Figure 19-9 is a timing diagram for duration threshold event counting.

MPC8540 Datasheet(PDF) 1089 Page - Freescale Semiconductor, Inc