MPC8540 datasheet(1088/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

19-10

Freescale Semiconductor

Performance Monitor

Figure 19-7. Performance Monitor Counter Register 0 (PMC0)

Table 19-7 describes PMC0 fields.

PMC1–PMC8, shown in Figure 19-8, are 32-bit counters that can monitor 64 unique events in

addition to the 64 reference events that can be counted on all of these registers.

Figure 19-8. Performance Monitor Counter Registers 1–8 (PMC1–PMC8)

Table 19-8 describes PMCn fields.

19.4 Functional Description

This section describes the use of some features of the performance monitor.

19.4.1 Performance Monitor Interrupt

PMCs can generate an interrupt on an overflow when the msb of a counter changes from 0 to 1.

For the interrupt to be signalled, the condition enable bit (PMLCAn[CE]) and performance

monitor interrupt enable bit (PMGC0[PMIE]) must be set. When an interrupt is signalled and the

031

PMC0 upper

PMC0 lower

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_1018

0xE_101C

Table 19-7. PMC0 Field Descriptions

Bits

Name

Description

0–63

PMC0 Event count. Counts only clock cycles

PMCn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_1028, 0xE_1038, 0xE_1048, 0xE_1058, 0xE_1068, 0xE_1078, 0xE_1088, 0xE_1098

Table 19-8. PMCn Field Descriptions

Bits

Name

Description

0–31

PMCn

Event count. An overflow is indicated when the msb = 1. Manually setting the msb can

cause an immediate interrupt.

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