MPC8540 datasheet(1084/1302 Pages) FREESCALE

1084 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

19-6

Freescale Semiconductor

Performance Monitor

Figure 19-3. Performance Monitor Local Control Register A0 (PMLCA0)

Table 19-3 describes PMLCA0 fields.

Figure 19-4 shows the performance monitor local control registers A1–A8.

Figure 19-4. Performance Monitor Local Control Registers A1–A8 (PMLCA1–PMLCA8)

Table 19-4 describes PMLCAn fields.

0000

000000

00000

000000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_1010

Table 19-3. PMLCA0 Field Descriptions

Bits

Name

Description

Freeze counter. Basic counter enable

0 The PMCs are enabled and incremented (if permitted by other SPM control bits).

1 The PMCs are disabled–they do not increment.

1–4

—

Reserved

Condition enable. Controls counter overflow condition. Should be cleared when PMC0 is used as a

trigger or is selected for chaining

0 Overflow conditions for PMC0 cannot occur (PMC0 cannot cause interrupts or freeze counters)

1 Overflow conditions occur when PMC0[msb] is set.

6–31

—

Reserved

1516

2021

2526

0000

EVENT

BSIZE

BGRAN

BDIST

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_1020, 0xE_1030, 0xE_1040, 0xE_1050, 0xE_1060, 0xE_1070, 0xE_1080, 0xE_1090

Table 19-4. PMLCA1–PMLC8 Field Descriptions

Bits

Name

Description

Freeze counter

0 The PMCs are incremented (if permitted by other PMC control bits).

1 The PMCs are not incremented (if permitted by other PMC control bits).

1–4

—

Reserved

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