MPC8540 datasheet(1073/1302 Pages) FREESCALE

1073 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-25

The column in Table 18-23 showing the global utilities block as initiating a low-power mode

corresponds to the external masters that can write to the POWMGTCSR that resides in the global

utilities block. For the MPC8540, these are the RapidIO and PCI/PCI-X interfaces. However, note

that the core can also write to POWMGTCSR and, in this case, can initiate power management

through the global utilities block.

As shown in Figure 18-20, the e500 core enters low-power modes only in response to the

core_halt, core_stop, or core_tben inputs from the MPC8540’s power management logic. These

inputs may be prompted by the core (by setting the NAP, DOZE, or SLEEP bits in the HID0 when

enabled by setting MSR[WE]) or by an external master (by setting POWMGTCSR[DOZ,SLP].

Figure 18-20 shows how all the clocking to the core timer facilities is disabled by clearing

HID0[TBEN]. When enabled, (HID0[TBEN] = 1), the clock source is either the CCB clock

divided by eight (the default) or a synchronized version of the RTC input. For more details, see

Section 6.10.1, “Hardware Implementation-Dependent Register 0 (HID0).”

Table 18-23. Power Management Entry Protocol and Initiating Functional Units

Low-

Power

Mode

Entry Protocol

Initiating Functional Unit

Global Utilities

Core

Doze

1. Assert core_halt input to core.

2. Wait for core_halted handshake from core.

√√

Nap

1. Follow doze protocol

2. Assert core_stop input to core.

3. Wait for core_stopped handshake from core.

—

√

Sleep

1. Follow doze protocol; send stop requests to rest of device.

2. Follow nap protocol.

3. Wait for all interfaces to acknowledge stop requests.

4. Assert ASLEEP, negate READY, power down all clocks except to PIC unit

√√

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