MPC8540 datasheet(1072/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-24

Freescale Semiconductor

Global Utilities

18.5.1.5.3 Sleep Mode

In sleep mode, all clocks internal to the e500 core are turned off, including the timer facilities

clock. All I/O interfaces in the device logic are also shut down. Only the clocks to the MPC8540

PIC are still running so that an external interrupt can wake up the device. Note that the DDR

controller does not shut down unless DDR_SDRAM_INTERVAL[REFINT] is set to a non-zero

value. See Section 9.4.1.7, “DDR SDRAM Interval Configuration

(DDR_SDRAM_INTERVAL),” for details.

After the core and I/O interfaces have shut down, ASLEEP is asserted and READY is negated.

NOTE

Only external interrupts can wake the MPC8540 from sleep mode.

Internal interrupt sources like the core interval timer or watchdog

timer depend on an active clock for their operation and these are

disabled in sleep mode.

18.5.1.6 Power Management Control Fields

The e500 core provides the following fields to signal power management requests to the MPC8540

device logic.

•

MSR[WE]—Used to qualify the values of HID0[DOZE,NAP,SLEEP] in the generation of

the internal doze, nap, and sleep signals

•

HID0[DOZE]—Signals the MPC8540 to initiate doze mode

•

HID0[NAP]—Signals the MPC8540 to initiate nap mode

•

HID0[SLEEP]—Signals the MPC8540 to initiate sleep mode

These register fields and their functional relationship are shown in Figure 18-20. The e500

Reference Manual has details on accessing these power management control bits.

An external master can also initiate power management requests by setting the DOZ or SLP bits

in the memory-mapped power management control and status register (POWMGTCSR). Because

the core responds to snoops while dozing but not while napping, maintaining cache coherency

requires significant preparation by the core before entering nap mode. For this reason only the core

can initiate a nap during normal operation while other masters can initiate a doze.

18.5.1.7 Power-Down Sequence Coordination

To preserve cache coherency and otherwise avoid loss of system state, the core’s transition to

low-power modes is coordinated by a set of handshaking signals, shown in Figure 18-20, and

protocols with all other MPC8540 functional blocks that respond to power-down requests. The

mode-transition protocol is executes automatically under these conditions and is shown in

Figure 18-19 and described in Table 18-23.

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