MPC8540 datasheet(1071/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-23

interrupts.) The results of re-enabling previously disabled blocks (by clearing the corresponding

DEVDISR field) without a hard reset are boundedly undefined.

NOTE

Functional blocks disabled using DEVDISR cannot respond to

configuration accesses. Any access to configuration, control, and

status registers of a disabled block is a programming error.

18.5.1.5 Software-Controlled Power-Down States

e500 software can place the device in doze, nap, or sleep power-down states by writing to HID0

in the core. In addition, external masters can write to the memory-mapped POWMGTCR in the

MPC8540 to cause the device to enter doze or sleep modes.

18.5.1.5.1 Doze Mode

In doze mode, the e500 core suspends instruction execution, significantly reducing the power

consumption of the core. Snooping of the L1 data cache is still supported and thus the data in the

data cache is kept coherent. Interrupts directed to the core as described in Section 10.1.3,

“Interrupts to the Processor Core,” are monitored by the device and cause the MPC8540 to use the

defined handshake mechanism to exit the core from doze mode to allow the core to recognize and

process the interrupt; however, unless the interrupt subroutine turns off (or masks) the control bits

that enabled doze mode (MSR[WE], and HID0[DOZE]), the device re-enters doze mode after the

interrupt has been serviced. See Section 18.5.1.8, “Interrupts and Power Management,” for more

information.

The e500 core’s timer facilities are still enabled during doze mode, and core time base interrupts

can be generated. All device logic external to the core remains fully operational in doze mode.

18.5.1.5.2 Nap Mode

In nap mode all clocks internal to the e500 core are turned off except for its timer facilities clock

(the core time base). The L1 caches do not respond to snoops in nap mode, so if coherency with

external I/O transactions is required, the L1 cache must be flushed before entering nap mode.

Similar to doze mode, interrupts occurring in nap mode cause the device to wake up the e500 core

in order to service the interrupt. However, unless the interrupt service routine changes the control

bits that caused the device to enter nap mode (MSR[WE], and HID0[NAP]), the MPC8540 returns

to nap mode after the interrupt is serviced. See Section 18.5.1.8, “Interrupts and Power

Management,” for more information.

All device logic external to the e500 core remains fully operational in nap mode.

MPC8540 Datasheet(PDF) 1071 Page - Freescale Semiconductor, Inc