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MPC8540 Datasheet(PDF) 1074 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1074 Page - Freescale Semiconductor, Inc |
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1074 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 18-26 Freescale Semiconductor Global Utilities Figure 18-20. MPC8540 Power Management Handshaking Signals MSR[WE] HID0[NAP] HID0[DOZE] HID0[SLEEP] sleep nap doze e500 Core Complex Device Logic core_halted core_stop core_halt core_tben Stop Fetching Instructions Instruction Execution Stopped? Yes No core_stopped Stop Clock Distribution Clock Distribution Stopped? Yes No HID0[SEL_TBCLK] 8 ÷ CCB Clock RTC (Sampled and synchronized) Snoopable Traffic Stopped? Yes No POWMGTCSR[DOZ] POWMGTCSR[SLP] Note: All signals shown are internal to the device. CKSTP_IN HRESET core_tbint Core Timer Facilities Core Timer Clock (Time Base) HID0[TBEN] Processor interrupt sources (see Table 10-2 and Table 10-3) DEVDISR[TB] DEVDISR[E500] Any transactions that are complete could have snooped |
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