MPC8540 datasheet(1070/1302 Pages) FREESCALE

1070 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-22

Freescale Semiconductor

Global Utilities

For each operating state represented in the diagram, the core’s state is listed first, with the

corresponding state of the MPC8540 shown beneath it in parenthesis. Note that there are many

other variables that control the state transitions between MPC8540 power management states.

These additional variables are described in more detail in Section 18.5.1.7, “Power-Down

Sequence Coordination.”

Table 18-22 lists basic characteristics of the low-power modes and the full on mode.

18.5.1.2 CKSTP_IN Is Not Power Management

CKSTP_IN is not described here because it is not considered a power management signal,

although asserting it does stop the core and a stopped core is technically in a low-power mode.

CKSTP_IN is described in Section 18.3.2, “Detailed Signal Descriptions.”

18.5.1.3 Dynamic Power Management

Many blocks in the MPC8540 can dynamically turn off clocks within the block when sections of

the block are idle. This feature is always enabled and occurs automatically.

18.5.1.4 Shutting Down Unused Blocks

As described in Section 18.4.1.11, “Device Disable Register (DEVDISR),” DEVDISR provides a

way to shut down certain functional blocks within the MPC8540 when they are not needed in a

particular system. DEVDISR can be written by the e500 core or by an external master. Powering

down a block in this way turns off all clocks to that block.

DEVDISR was designed with the expectation that, once initialized by software, it would be

modified only by a hard system reset (HRESET). It is recommended that this register be written

only during system initialization. Blocks disabled by DEVDISR must not be re-enabled without a

hard reset. (Setting DEVDISR[TB] disables the core’s timer facilities, and setting

DEVDISR[E500] places the core in the core-stopped state in which it does not respond to

Table 18-22. MPC8540 Power Management Modes—Basic Description

Mode

Description

Core Responds To

Signal States

Snoop

Interrupts READY ASLEEP

Full On

All units operating normally

Yes

Asserted Negated

Doze

Core stops dispatching new instructions (core is halted)

Yes

Negated Negated

Nap

Core is stopped with clocks off except to time base

Should flush data cache before entering

Yes

Negated Negated

Sleep

Core is stopped with clocks off. Clocks powered down to all

blocks (including core time base) except to the interrupt

controller (PIC) unit

Yes

Negated Asserted

MPC8540 Datasheet(PDF) 1070 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1070 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL