MPC8540 datasheet(1066/1302 Pages) FREESCALE

1066 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-18

Freescale Semiconductor

Global Utilities

Table 18-17 describes the fields of PVR.

18.4.1.15 System Version Register (SVR)

Shown in Figure 18-15, the SVR contains the system version number for the MPC8540

implementation. This value can also be read though the SVR SPR of the e500 core. See

Section 6.5.4, “System Version Register (SVR).” Section 5.2, “e500 Processor and System

Version Numbers,” lists the complete values for the MPC8540.

Table 18-18 describes the fields of SVR.

18.4.1.16 Clock Out Control Register (CLKOCR)

Shown in Figure 18-16, the CLKOCR contains control bits that select the clock sources to be

placed on the clock out (CLK_OUT) signal.

Table 18-17. PVR Field Descriptions

Bits

Name

Description

0–15

Version

A 16-bit number that identifies the version of the processor. Different version numbers indicate major

differences between processors, such as which optional facilities and instructions are supported.

16–31 Revision A 16-bit number that distinguishes between implementations of the version. Different revision

numbers indicate minor differences between processors having the same version number, such as

clock rate and engineering change level.

System Version

Reset

0x8030_nnnn

Offset

0xE_00A4

Figure 18-15. System Version Register (SVR)

Table 18-18. SVR Field Descriptions

Bits

Name

Description

0–31

System version for the MPC8540 system logic

ENB

0 0 0 0 0 0 0 000 00 00 00 00 00 000 00 00 00

CLK_SEL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_0E00

Figure 18-16. Clock Out Control Register (CLKOCR)

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