MPC8540 datasheet(1065/1302 Pages) FREESCALE

1065 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-17

For more information about RFXE, see Section 6.10.2, “Hardware Implementation-Dependent

Figure 18-13. Machine Check Summary Register (MCPSUMR)

Table 18-16 describes the bit settings of MCPSUMR.

18.4.1.14 Processor Version Register (PVR)

Shown in Figure 18-14, the PVR contains the e500 processor version number. It is a

memory-mapped copy of the PVR in the e500 core (and is therefore accessible to external

devices). See Section 6.5.3, “Processor Version Register (PVR).” Section 5.2, “e500 Processor

and System Version Numbers,” lists the complete values for the MPC8540.

R 000000000000000000

0 0000000000

WRS SRESET MCP_IN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_0090

Table 18-16. MCPSUMR Field Descriptions

Bits

Name

Description

0–28

—

Reserved

WRS

Watchdog timer machine check

0 Machine check exception was not caused by watchdog timer

1 Machine check was caused by a soft reset condition from the e500 watchdog timer as configured

in the core’s TSR. Specifically, TSR[WRS] = 01 and a watchdog reset condition occurred.

SRESET Soft reset machine check

0 Machine check exception was not caused by SRESET assertion

1 Machine check exception was caused by the assertion of the SRESET input signal

MCP_IN MCP signal asserted

0 Machine check exception was not caused by MCP assertion

1 Machine check exception was caused by the assertion of the MCP input signal

015 16

Version

Revision

Reset

0x8020_nnnn

Offset

0xE_00A0

Figure 18-14. Processor Version Register (PVR)

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