MPC8540 datasheet(1062/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-14

Freescale Semiconductor

Global Utilities

All functional blocks are enabled after reset; unneeded blocks can be disabled to reduce power

consumption or allow their signals to be used as general-purpose I/O signals. See Section 18.4.1.7,

“General-Purpose I/O Control Register (GPIOCR).” Blocks disabled by DEVDISR must not be

re-enabled without a hard reset. Section 18.5.1.4, “Shutting Down Unused Blocks,” has more

information on the use of DEVDISR. Table 18-14 describes DEVDISR fields.

Table 18-14. DEVDISR Field Descriptions

Bits

Name

Description

PCI

PCI/PCI-X controller disable

0 PCI/PCI-X controller enable

1 PCI_AD[63:32] may be used as general-purpose I/O

1–3

—

Reserved

LBC

Local bus controller disable

0 Local bus controller enable

1 Local bus controller disable

5–10

—

Reserved

Level-2 cache disable

0 L2 cache enable

1 L2 cache disable

RIO

RapidIO controller disable

0 RapidIO controller enable

1 RapidIO controller disable, including RapidIO messaging, doorbell, and port write controllers.

13–14

—

Reserved

DDR

DDR SDRAM controller disable

0 DDR SDRAM controller enable

1 DDR SDRAM controller disable

E500

e500 core disable

0 e500 core enable

1 e500 core disable. Places the core in the core-stopped state in which it does not respond to

interrupts. Equivalent to nap mode. Instruction fetching is stopped, snooping is disabled, and

clocks are shut down to all functional units of the core except for the timer facilities.

For more information, see Section 18.5.1.4, “Shutting Down Unused Blocks.”

Time base (timer facilities) of the e500 core disable

0 Timer facilities enabled

1 Timer facilities disabled

18–20

—

Reserved

DMA

DMA controller disabled

0 DMA controller enabled

1 DMA controller disabled

22–23

—

Reserved

TSEC1 Three-speed Ethernet controller 1 disable

0 TSEC1 enabled

1 TSEC1 disabled

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