MPC8540 datasheet(1060/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-12

Freescale Semiconductor

Global Utilities

18.4.1.9 General-Purpose Input Data Register (GPINDR)

GPINDR, shown in Figure 18-9, contains the data currently sampled as general-purpose input on

TSEC2_RxD[0:7] and/or PCI_AD[39:32] when either of these buses is configured as

general-purpose I/O buses in GPIOCR (see Section 18.4.1.7, “General-Purpose I/O Control

general-purpose input pins rather than their primary functions.

Table 18-11 describes the fields of GPINDR.

18.4.1.10 Alternate Function Signal Multiplex Control Register (PMUXCR)

Shown in Figure 18-10, PMUXCR contains bits that enable DMA channels 2 and 3 which exist as

alternate functions on local bus chip select pins LCS[5:7], and interrupt input pins IRQ[9:11],

respectively. Specifically, DMA request, acknowledge, and done signals comprise the secondary

functions for the associated IRQ and local bus chip select signals.

015 16

GPIN

0000

00000

0000

Reset

nnnn_nnnn_nnnn_nnnn_0000_0000_0000_0000

Offset

0xE_0050

Figure 18-9. General-Purpose Output Data Register (GPINDR)

Table 18-12. GPINDR Field Descriptions

Bits

Name

Description

0–15

GPIN General-purpose input data. When the corresponding signals are configured to be general-purpose

input signals, the values sampled on these signals are reflected in GPIN. GPINDR[0:7] corresponds to

TSEC2_RxD[0:7]. GPINDR[8:15] corresponds to PCI_AD[39:32] as follows:

GPINDR[8]

↔ PCI_AD[39]

GPINDR[9]

↔ PCI_AD[38]

GPINDR[10]

↔ PCI_AD[37]

GPINDR[11]

↔ PCI_AD[36]

GPINDR[12]

↔ PCI_AD[35]

GPINDR[13]

↔ PCI_AD[34]

GPINDR[14]

↔ PCI_AD[33]

GPINDR[15]

↔ PCI_AD[32]

16–31

—

Reserved

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