MPC8540 datasheet(1056/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-8

Freescale Semiconductor

Global Utilities

Table 18-7 describes the bit settings of PORDEVSR.

1516

28 2931

R ECW 000 00 ECP PCI 00 00 0 PCI_ARB PCI32 0 0 0 0 0 0 RIOCLK 0 000 0 DEV_ID

Reset

n000_00nn_n000_00nn_0000_00nn_0000_0nnn

Offset

0xE_000C

Figure 18-4. POR Device Status Register (PORDEVSR)

Table 18-7. PORDEVSR Field Descriptions

Bits

Name

Description

ECW

Gigabit Ethernet controller width

0 Reduced (RGMII, RTBI)

1 Full (MII, GMII, TBI)

1–5

—

Reserved

6-7

ECP

Gigabit Ethernet controller protocol

00 Both TSEC blocks use a Media Independent Interface protocols (MII/GMII/RGMII)

01 TSEC1 uses MII, TSEC2 uses TBI

10 TSEC1 uses TBI, TSEC2 uses MII

11 Both TSEC blocks use a ten bit interface protocol (TBI or RTBI)

PCI

PCI/PCI-X mode

0 PCI-X mode

1 PCI mode

9–13

—

Reserved

PCI_ARB PCI/PCI-X arbiter enable

0 PCI/PCI-X arbiter is disabled

1 PCI/PCI-X arbiter is enabled

PCI32

PCI/PCI-X interface width

0 64-bit

1 32-bit

16–21

—

Reserved

22–23

RIOCLK

RapidIO transmit clock source

00 Reserved

01 RapidIO receive clock

10 RapidIO transmit clock input

11 CCB clock (default)

24–28

—

Reserved

29–31

DEV_ID

RapidIO device ID [5:7]

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