MPC8540 datasheet(1054/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-6

Freescale Semiconductor

Global Utilities

18.4.1.3 POR I/O Impedance Status and Control Register (PORIMPSCR)

PORIMPSCR, shown in Figure 18-3,contains the current I/O driver impedances for local bus and

PCI interfaces.

The I/O impedance of local bus signals (including the local bus clock) is controlled through this

Table 18-5. PORBMSR Field Descriptions

Bits

Name

Description

BCFG

CPU boot configuration

0 The CPU is prevented from booting until configuration by an external master is complete.

1 The CPU is allowed to start fetching boot code.

1–4

—

Reserved

5–7

ROM_LOC Location of boot ROM:

000 PCI/PCI-X

001 DDR SDRAM

011 RapidIO

101 Local bus GPCM: 8-bit

110 Local bus GPCM:16-bit

111 Local bus GPCM: 32-bit

8–9

—

Reserved

10–11

BSCFG

Boot sequencer configuration

00 Reserved

01 Boot sequencer enabled with normal I2C addressing

10 Boot sequencer enabled with extended I2C addressing

11 Boot sequencer disabled

12–13

—

Reserved

14–15

Host/agent mode configuration. When the MPC8540 is an agent on an interface, it is prevented

from mastering transactions on that interface until the external host configures the interface

appropriately.

00 PCI and RapidIO agent mode

01 RapidIO agent mode

10 PCI/PCI-X agent mode

11 Host mode

16–31

—

Reserved

141516

R 0 00 000 0000 0000 0 PCI_Z 0 0 0 000 00 0

LALE_Z LADP_Z LA_CKE_Z LCS12_Z LWE_Z LGPL_Z LCLK_Z

Reset

0000_0000_0000_000n_0000_0000_0111_1111

Offset

0xE_0008

Figure 18-3. POR I/O Impedance Status and Control Register (PORIMPSCR)

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