MPC8540 datasheet(1055/1302 Pages) FREESCALE

1055 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-7

Section 4.4.3.13, “PCI I/O Impedance.”) The MPC8540 Integrated Processor Hardware

Specifications provides exact I/O impedances.

Table 18-6 describes PORIMPSCR fields.

18.4.1.4 POR Device Status Register (PORDEVSR)

Shown in Figure 18-4, PORDEVSR reports other POR settings for I/O devices as described in

Section 4.4.3.7, “TSEC Width,” Section 4.4.3.8, “TSEC1 Protocol,” Section 4.4.3.9, “TSEC2

Protocol,” Section 4.4.3.16, “PCI-X Configuration,” Section 4.4.3.14, “PCI Arbiter

Configuration,” Section 4.4.3.12, “PCI Width Configuration,” Section 4.4.3.10, “RapidIO

Transmit Clock Source,” and Section 4.4.3.11, “RapidIO Device ID.”

Table 18-6. PORIMPSCR Field Descriptions

Bits

Name

Description

0–14

—

Reserved

PCI_Z

PCI/PCI-X I/O impedance

0 Low impedance

1 High impedance

16–24

—

Reserved

LALE_Z

I/O impedance for local bus address latch enable

0 Low impedance

1 High impedance

LADP_Z

I/O impedance for local bus address/data and data parity (LAD[0:31] and LDP[0:7])

0 Low impedance

1 High impedance

LA_CKE_Z

I/O impedance for local bus address and clock enable (LA[27:31] and LCKE)

0 Low impedance

1 High impedance

LCS12_Z

I/O impedance for two local bus chip selects (LCS[1] and LCS[2] only).

NOTE: Other chip selects use a fixed high I/O impedance

0 Low impedance

1 High impedance

LWE_Z

I/O impedance for local bus write enables (LWE[0:3])

0 Low impedance

1 High impedance

LGPL_Z

I/O impedance for local bus general-purpose lines (LGPL[0:5])

0 Low impedance

1 High impedance

LCLK_Z

I/O impedance for local bus clocks (LCLK[0:2])

0 Low impedance

1 High impedance

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