MPC8540 datasheet(1053/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-5

Table 18-4 describes the bit settings of PORPLLSR.

18.4.1.2 POR Boot Mode Status Register (PORBMSR)

The PORBMSR, shown in Figure 18-2, reports setting of the POR configuration pins that control

the boot mode settings (described in Section 4.4.3.3, “Boot ROM Location,” Section 4.4.3.5,

“CPU Boot Configuration,” and Section 4.4.3.6, “Boot Sequencer Configuration,”) and the

default settings of RapidIO and PCI host/agent modes (described in Section 4.4.3.4, “Host/Agent

Configuration”).

For information about how the RapidIO interface is configured, see Section 17.3.1.19, “Port

General Control Command and Status Register (PGCCSR).” For more information about the PCI

configurations, see Section 16.3.2.19, “PCI Bus Function Register (PBFR).” Figure 18-5

describes the bit settings of the PORBMSR.

Table 18-4. PORPLLSR Field Descriptions

Bits

Name

Description

0–9

—

Reserved

10–15 e500_Ratio Clock ratio between the e500 core and the CCB clock. The 2 lsbs of this field correspond to the

values on cfg_core_pll[0:1] at the negation of HRESET. Patterns not shown are reserved.

0001002:1

0001015:2

0001103:1

0001117:2

16–25

—

Reserved

26–30

Plat_Ratio

Clock ratio between the CCB (platform) clock and SYSCLK. The 4 lsbs correspond to the values

on cfg_sys_pll[0:3] at the negation of HRESET. Patterns not shown are reserved.

000102:1

000113:1

001004:1

001015:1

001106:1

010008:1

010019:1

0101010:1

0110012:1

1000016:1

—

Reserved

1213 1415 16

R BCFG 0 0 0 0 ROM_LOC 0

0 BSCFG 0

0 00 00 00 00 00 0 0 0

Reset

n000_0nnn_00nn_00nn_0000_0000_0000_0000

Offset

0xE_0004

Figure 18-2. POR Boot Mode Status Register (PORBMSR)

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