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MPC8540 Datasheet(PDF) 1052 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1052 Page - Freescale Semiconductor, Inc |
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1052 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 18-4 Freescale Semiconductor Global Utilities 18.4.1 Register Descriptions This section describes the global utilities registers in detail. 18.4.1.1 POR PLL Status Register (PORPLLSR) PORPLLSR, shown in Figure 18-1, contains the settings for the PLL ratios as set by the cfg_sys_pll[0:3] and cfg_core_pll[0:1] POR configuration pins. See Section 4.4.3.1, “System PLL Ratio,” and Section 4.4.3.2, “e500 Core PLL Ratio,” for more information. Figure 18-1. POR PLL Status Register (PORPLLSR) 0xE_0050 GPINDR—General-purpose input data register R 0xnnnn_0000 18.4.1.9/18-12 0xE_0060 PMUXCR—Alternate function signal multiplex control R/W 0x0000_0000 18.4.1.9/18-12 Device Disables 0xE_0070 DEVDISR—Device disable control R/W 0x0000_0000 18.4.1.11/18-13 Power Management Registers 0xE_0080 POWMGTCSR—Power management status and control register R/W 0x0000_0000 18.4.1.12/18-15 Interrupt Reporting 0xE_0090 MCPSUMR—Machine check summary register Read/Clear 0x0000_0000 18.4.1.13/18-16 Version Registers 0xE_00A0 PVR—Processor version register R e500 processor version 18.4.1.14/18-17 0xE_00A4 SVR—System version register R MPC8540 system version 18.4.1.15/18-18 Debug Control 0xE_0E00 CLKOCR—Clock out select register R/W 0x0000_0000 18.4.1.16/18-18 0xE_0E10 DDRDLLCR—DDR DLL control register R/W 0x0000_0000 18.4.1.17/18-19 0xE_0E20 LBDLLCR—LBC DLL control register R/W 0x0000_0000 18.4.1.18/18-20 0 9 10 15 16 25 26 30 31 R 0 0 0 0 0 0 0 0 0 0 e500_Ratio 0 0 0 0 0 0 0 0 0 0 Plat_Ratio 0 W Reset 0000_0000_00nn_nnnn_0000_0000_00nn_nnnn Offset 0xE_0000 Table 18-3. Global Utilities Block Register Summary (continued) Offset Register Access Reset Section/Page |
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