MPC8540 datasheet(1051/1302 Pages) FREESCALE

1051 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-3

18.4 Memory Map/Register Definition

Table 18-3 summarizes the global utilities registers and their addresses.

CKSTP_IN

Checkstop in

State

Meaning

Asserted—Indicates that the e500 core must enter a hard stop condition. All e500 clocks

are turned off. CKSTP_OUT is asserted. The rest of MPC8540 device logic,

including memory controllers, internal memories and registers, and I/O interfaces,

remains functional.

Negated—Indicates that normal operation should proceed

Timing

Assertion—May occur at any time; may be asserted asynchronously to the input clocks

Negation—Must remain asserted until the MPC8540 is reset with assertion of HRESET

CKSTP_OUT

Checkstop out

State

Meaning

Asserted—Indicates that the e500 core of the MPC8540 is in a checkstop state. The rest

of the MPC8540 logic remains functional.

Negated—Indicates normal operation. After CKSTP_OUT has been asserted, it is

negated after the next negation (low-to-high transition) of HRESET.

Timing

Assertion—May occur at any time; may be asserted asynchronously to the input clocks

Negation—Must remain asserted until the device has been reset with a hard reset

CLK_OUT

Clock out. Reflects clock signal selected by CLKOCR (see Section 18.4.1.16, “Clock Out Control

State

Meaning

Asserted—If CLKOCR[ENB] = 1, clock signal selected by CLKOCR[CLK_SEL] is driven

High impedance—If CLKOCR[ENB] = 0

Timing

Assertion/Negation—Depends on the value of CLKOCR[CLK_SEL]

Table 18-3. Global Utilities Block Register Summary

Offset

Access

Reset

Section/Page

Power-On Reset Configuration Values

0xE_0000 PORPLLSR—POR PLL ratio status register

0x00nn_00nn

18.4.1.1/18-4

0xE_0004 PORBMSR—POR boot mode status register

0xnnnn_0000

18.4.1.2/18-5

0xE_0008 PORIMPSCR—POR I/O impedance status and control register

R/W

0x000n_007F

18.4.1.3/18-6

0xE_000C PORDEVSR—POR I/O device status register

See ref.

18.4.1.4/18-7

0xE_0010 PORDBGMSR—POR debug mode status register

See ref.

18.4.1.5/18-9

0xE_0020 GPPORCR—General-purpose POR configuration register

See ref.

18.4.1.6/18-9

Signal Multiplexing and GPIO Controls

0xE_0030 GPIOCR—GPIO control register

R/W

0x0000_0000 18.4.1.7/18-10

0xE_0040 GPOUTDR—General-purpose output data register

R/W

0x0000_0000 18.4.1.8/18-11

Table 18-2. Detailed Signal Descriptions (continued)

Signal

I/O

Description

MPC8540 Datasheet(PDF) 1051 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1051 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL