MPC8540 datasheet(1057/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-9

18.4.1.5 POR Debug Mode Status Register (PORDBGMSR)

PORDBGMSR, shown in Figure 18-5, holds debug mode settings from the POR configuration

pins as described in Section 4.4.3.17, “Memory Debug Configuration,” Section 4.4.3.18, “DDR

Debug Configuration,” and Section 4.4.3.15, “PCI Debug Configuration.”

Table 18-8 describes the bit settings of PORDBGMSR.

18.4.1.6 General-Purpose POR Configuration Register (GPPORCR)

Shown in Figure 18-6, GPPORCR stores the value sampled from the local bus address/data

signals, LAD[0:31], during POR, as described in Section 4.4.3.21, “General-Purpose POR

Configuration.” Software can use this value to inform the operating system about initial system

configuration. Typical interpretations include circuit board type, board ID number, or a list of

available peripherals.

R 0 0 0 0 0 MEM_SEL DDR_DBG PCI_DBG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset

0000_0nnn_0000_0000_0000_0000_0000_0000

Offset

0xE_0010

Figure 18-5. POR Debug Mode Status Register (PORDBGMSR)

Table 18-8. PORDBGMSR Field Descriptions

Bits

Name

Description

0–4

—

Reserved

MEM_SEL Memory select. Indicates which controller is driving MSRCID[0:4] and MDVAL

0 Local bus controller is driving debug information

1 DDR SDRAM controller is driving debug information

DDR_DBG DDR debug configuration

0 SourceID and data valid information is being driven on ECC pins of DDR SDRAM interface

1 Normal mode. ECC information is being driven on ECC pins of DDR SDRAM interface

PCI_DBG

PCI/PCI-X debug configuration

0 PCI/PCI-X drives source ID onto PCI_AD[62:58].

1 PCI/PCI-X drives address/data 62:58 onto PCI_AD[62:58].

8–31

—

Reserved

POR_CFG_VEC

Reset

0xnnnn_nnnn

Offset

0xE_0020

Figure 18-6. POR Configuration Register (GPPORCR)

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