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MPC8540 Datasheet(PDF) 1061 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1061 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
18-13
Table 18-13 describes the bit settings of PMUXCR.
18.4.1.11 Device Disable Register (DEVDISR)
DEVDISR, shown in Figure 18-11, contains disable bits for various MPC8540 functional blocks.
0
14
1516
3031
R 0
00 00 00 00 000 00
0
DMA2
0
0 0 0 0 0 00 00 00 00
0
DMA3
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xE_0060
Figure 18-10. Alternate Function Pin Multiplex Control Register (PMUXCR)
Table 18-13. PMUXCR Field Descriptions
Bits
Name
Description
0–14
—
Reserved
15
DMA2
Enables DMA channel 2 signals
0 DMA channel 2 is disabled; the pins retain their primary function as local bus chip selects
1 DMA channel 2 is enabled and
LCS5 functions as DMA_DREQ2
LCS6 functions as DMA_DACK2
LCS7 functions as DMA_DDONE2
16–30
—
Reserved
31
DMA3
Enables DMA channel 3 signals
0 DMA channel 3 is disabled; the pins retain their primary function as interrupt requests.
1 DMA channel 3 is enabled and
IRQ9 functions as DMA_DREQ3
IRQ10 functions as DMA_DACK3
IRQ11 functions as DMA_DDONE3
01
3
4
5
10
11
12
13
14
15
R
PCI
00
0
LBC
00
0
0
0
0
L2
RIO
00
DDR
W
Reset
0000_0000_0000_0000
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
R
E500
TB
0
0
0
DMA
00
TSEC1 TSEC2
FEC
00
I2C DUART
0
W
Reset
0000_0000_0000_0000
Offset
0xE_0070
Figure 18-11. Device Disable Register (DEVDISR)



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