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MPC8540 Datasheet(PDF) 1063 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1063 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
18-15
18.4.1.12 Power Management Control and Status Register (POWMGTCSR)
Shown in Figure 18-12, POWMGTCSR contains bits for placing the MPC8540 into low power
states and for controlling when it wakes up. It also contains power management status bits. See
Section 18.5.1.8.2, “Interrupts and Power Management Controlled by POWMGTCSR,” for more
information.
Table 18-15 describes the bit settings of POWMGTCSR.
25
TSEC2 Three-speed Ethernet controller 2 disable
0 TSEC2 enabled
1 TSEC2 disabled. RxD and TxD pins may be used for general-purpose I/O
26
FEC
Fast Ethernet controller (10/100 maintenance port) disable
0 FEC enabled
1 FEC disabled
27–28
—
Reserved
29
I2C
I2C controller disabled
0I2C controller enabled
1I2C controller disabled
30
DUART Dual UART controller disabled
0 DUART enabled
1 DUART disabled
31
—
Reserved
01
2
11
12
13
14
15
27
28
29
30
31
R
IRQ_MSK CI_MSK
0 000 000 00 0
DOZ
0
SLP
0 0 0 0 0 0 0 0 0 0 0 0 0 DOZING NAPPING SLPING 0
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xE_0080
Figure 18-12. Power Management Control and Status Register (POWMGTCSR)
Table 18-15. POWMGTCSR Field Descriptions
Bits
Name
Description
0
IRQ_MSK Interrupt input mask
0 Interrupts cause the device to wake up from a low-power state.
1 Interrupts are masked as a wake-up condition. The device remains in a low-power state despite
the presence of an interrupt request.
1
CI_MSK
Critical interrupt input mask
0 Critical interrupts cause the device to wake up from a low power state.
1 Critical interrupts are masked as a wake-up condition. The device remains in a low-power state
despite the presence of a critical interrupt.
Table 18-14. DEVDISR Field Descriptions (continued)
Bits
Name
Description



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