MPC8540 datasheet(1067/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-19

Table 18-19 describes the bit settings of CLKOCR.

18.4.1.17 DDR DLL Control Register (DDRDLLCR)

The DDRDLLCR, shown in Figure 18-17, contains bits that allow control and debug of the DDR

SDRAM controller’s DLL. The DLL delay chain consists of 128 tap points.

Table 18-20 describes the bit settings of DDRDLLCR.

Table 18-19. CLKOCR Field Descriptions

Bits

Name

Description

ENB

Clock out enable

0 CLK_OUT signal is tri-stated

1 CLK_OUT signal is driven according to CLKOCR[CLK_SEL]

1–29

—

Reserved

30–31

CLK_SEL Clock out select

00 CCB (platform) clock

01 CCB (platform) clock divided by 2

10 SYSCLK (echoes SYSCLK input)

11 SYSCLK divided by 2 (demonstrates platform PLL lock)

15 16

OVRD

000 0

COURSE_ADJ

TAP_SEL

0 0 0 0 0 COURSE_SET

TAP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0xE_0E10

Figure 18-17. DDR DLL Control Register (DDRDLLCR)

Table 18-20. DDRDLLCR Field Descriptions

Bits

Name

Description

OVRD

Override mode

0 Override mode disabled

1 Override of current delay chain tap point with the TAPSEL tap point enabled

1–4

—

Reserved

5–7

COURSE_ADJ Course adjustment value to be used by the DLL when in override mode (OVRD = 1). The

course adjustment is the number of CCB (platform) clock cycles of delay to inject before the

delay chain. When leaving override mode (OVRD cleared), this course adjustment point

serves as the starting point for a dynamic search for a lock point.

8–15

TAP_SEL

TAP select value to be used by the DLL when in override mode (OVRD = 1). Selects the tap

point within the delay chain. When leaving override mode (OVRD cleared) this tap point

serves as the starting point for a dynamic search for a lock point.

16–20

—

Reserved

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