MPC8540 datasheet(1069/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

18-21

18.5 Functional Description

This section describes the global utilities from a functional perspective.

18.5.1 Power Management

The MPC8540 has features to minimize power consumption at several levels. Dynamic power

management locally minimizes power consumption when a block is idle. Software can also shut

down clocks to individual blocks when they are not needed through a memory-mapped register

(DEVDISR). Additionally, software running on the e500 core can access the core’s SPRs to put

the device into doze, nap, or sleep power down state. Finally, software can access a

memory-mapped register (POWMGTCR) in the global utilities block to put the device in the doze

or sleep states.

Note that the software that writes to either DEVDISR or POWMGTCR can be running either on

the e500 core or on an external master that can write to the MPC8540 memory-mapped registers

through the RapidIO or PCI interfaces.

These features are described in further detail in this section.

18.5.1.1 Relationship Between Core and Device Power Management States

The MPC8540 has three low-power states: doze, nap, and sleep. The mapping of core and device

power management states is shown in Figure 18-19 showing state transitions from the perspective

of the e500 core.

Figure 18-19. e500 Core Power Management State Diagram

Core-Halted

Core-Stopped

core_halt & ¬core_stop

core_stop

¬core_halt

core_halt

¬core_stop

core_stop & core_halt

Full On

¬core_halt

(Doze)

(Nap)

Core-Stopped

¬core_tben

(Sleep)

¬core_tben

core_tben

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