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MPC8540 Datasheet(PDF) 1068 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1068 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
18-20
Freescale Semiconductor
Global Utilities
18.4.1.18 Local Bus DLL Control Register (LBDLLCR)
Shown in Figure 18-18, the LBDLLCR contains control bits that allow debug of the local bus
controller’s DLL. The delay chain of the DLL is made up of 128 tap points.
Table 18-21 describes the bit settings of LBDLLCR.
21–23 COURSE_SET Reports the current course delay setting found by the dynamic search algorithm that
produced a lock. Measured in CCB clock cycles
24–31
TAP
Reports the tap value found by the dynamic search algorithm that produced a lock.
Measured in tap points
0
1
4
5
7
8
15 16
20
21
23
24
31
R
OVRD
000 0
COURSE_ADJ
TAP_SEL
0 0 0 0 0 COURSE_SET
TAP
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0xE_0E20
Figure 18-18. Local Bus DLL Control Register (LBDLLCR)
Table 18-21. LBDLLCR Field Descriptions
Bits
Name
Description
0
OVRD
Override mode
0 Override mode disabled
1 Override of current delay chain tap point with the TAPSEL tap point enabled
1–4
—
Reserved
5–7
COURSE_ADJ Course adjustment value to be used by the DLL when in override mode (OVRD = 1). The
course adjustment is the number of CCB clock cycles of delay to inject before the delay chain.
When leaving override mode (OVRD cleared) this course adjust point serves as the starting
point for a dynamic search for a lock point.
8–15
TAP_SEL
TAP select value to be used by the DLL when in override mode (OVRD = 1). Selects the tap
point within the delay chain. When leaving override mode (OVRD cleared) this tap point
serves as the starting point for a dynamic search for a lock point.
16–20
—
Reserved
21–23 COURSE_SET Reports the current course delay setting found by the dynamic search algorithm that
produced a lock. Measured in CCB clock cycles
24–31
TAP
Reports the tap value found by the dynamic search algorithm that produced a lock. Measured
in tap points
Table 18-20. DDRDLLCR Field Descriptions (continued)
Bits
Name
Description



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