MPC8540 datasheet(1064/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

18-16

Freescale Semiconductor

Global Utilities

18.4.1.13 Machine Check Summary Register (MCPSUMR)

Shown in Figure 18-13, MCPSUMR contains bits summarizing some of the sources of a pending

machine check interrupt. All MCPSUMR bits function as write-one-to-clear.

NOTE

writing ones to them. Writing zeros to them has no effect.

Note that other conditions can cause a machine check condition not summarized in MCPSUMR.

For example, uncorrectable read errors cause the assertion of core_fault_in, which may directly

cause a machine check (if HID1[RFXE] = 1). If RFXE = 0, the assertion of core_fault_in does not

directly cause a machine check interrupt, but must be handled by the block that generated the error.

2–11

—

Reserved

DOZ

Doze mode

0 No request to put device in doze mode. Note that this bit is automatically cleared on MCP, UDE,

SRESET, core_tbint (from the core) and also int and cint if not masked.

1 Device is to be placed in doze mode. Instruction fetching is halted in the e500 core. Note that

this bit is logically ORed with HID0[DOZE].

—

Reserved

SLP

Sleep mode

0 No request to put device in sleep mode

1 Device is to be placed in sleep mode. Instruction fetching is halted, snooping of L1 caches is

disabled, and most functional blocks are shut down in both the e500 core and the system logic.

15–27

—

Reserved

DOZING

Doze status

0 Device is not in doze mode

1 The MPC8540 is in doze mode because POWMGTCSR[DOZ] is set or because HID0[DOZE]

and MSR[WE] (in the e500 core) are set. The core has halted instruction fetching, but all other

functional blocks in the core and device are running.

NAPPING Nap status

0 Device is not in nap mode.

1 The MPC8540 is in nap mode because HID0[NAP] and MSR[WE] are set. The core has halted

instruction fetching, snooping of the L1 caches is disabled, and all of the core’s functional units

except the timer facilities are shut down. All functional blocks in the device are running.

SLPING

Sleep status

0 Device is not attempting to reach sleep mode.

1 The device is attempting to SLEEP because POWMGTCSR[SLP] is set or because

HID0[SLEEP] and MSR[WE] (in the e500 core) are set. Most functional blocks in the core and

device are shut down or are attempting to shut down.

—

Reserved. Should be cleared.

Table 18-15. POWMGTCSR Field Descriptions (continued)

Bits

Name

Description

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